Hitachi SH7750 Hardware Manual page 79

Table 1.3 Pin Functions (cont)
Pin
No. Pin Name I/O
168 SCK2/ I
MRESET
169 VDD Power
170 VSS Power
171 A18 O
172 A19 O
173 A20 O
174 A21 O
175 A22 O
176 A23 O
177 VDDQ Power
178 VSSQ Power
179 A24 O
180 A25 O
181 MD3/CE2A I/O
182 MD4/CE2B I/O
183 MD5/RAS2 I/O
184 DACK0 O
185 DACK1 O
186 A0 O
187 VDDQ Power
188 VSSQ Power
189 A1 O
190 STATUS0 O
191 STATUS1 O
192 MD6/ I
IOIS16
ASEBRK/
193 I/O
BRKACK
Function Reset
MRESET SCK2
SCIF clock/
manual reset
Internal VDD
Internal GND
(0 V)
Address
Address
Address
Address
Address
Address
IO VDD (3.3 V)
IO GND (0 V)
Address
Address
Mode/ MD3
PCMCIA-CE
Mode/ MD4
PCMCIA-CE
Mode/RAS MD5
(DRAM)
DMAC0 bus
acknowledge
DMAC1 bus
acknowledge
Address
IO VDD (3.3 V)
IO GND (0 V)
Address
Status
Status
Mode/IOIS16 MD6
(PCMCIA)
Pin break/
acknowledge
)
(H-UDI
Memory Interface
SRAM DRAM SDRAM PCMCIA MPX
SCK2 SCK2
RAS2
Rev. 6.0, 07/02, page 29 of 986
SCK2 SCK2
CE2A
CE2B
IOIS16