Figure 13.18 Dram Wait State Timing - Hitachi SH7750 Hardware Manual

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Wait State Control: As the clock frequency increases, it becomes impossible to complete all

states in one cycle as in basic access. Therefore, provision is made for state extension by using the

setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in

figure 13.18. Additional Tpc cycles (cycles used to secure the RAS precharge time) can be

inserted by means of the TPC bit in MCR, giving from 1 to 7 cycles. The number of cycles from

RAS assertion to CAS assertion can be set to between 2 and 5 by inserting Trw cycles by means of

the RCD bit in MCR. Also, the number of cycles from CAS assertion to the end of the access can

be varied between 1 and 16 according to the setting of A2W2 to A2W0 or A3W2 to A3W0 in

(SA: IO ← memory)

(SA: IO → memory)

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.18 DRAM Wait State Timing

Rev. 6.0, 07/02, page 401 of 986

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