Hitachi SH7750 Hardware Manual page 504

Tpci2 Tpci2w
Tpci0 Tpci Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci1w
CKIO
A25–A1
A0
( )
RD/
( )
(read)
D15–D0
(read)
( )
(write)
D15–D0
(write)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.55 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface
Rev. 6.0, 07/02, page 454 of 986