Figure 22.19 Burst Rom Bus Cycle (No Wait) - Hitachi SH7750 Hardware Manual

CKIO
A25–A5
A4–A0
RD/
D31–D0
(read)
DACKn
(SA: IO ← memory)
DACKn
(DA)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
T1 TB2 TB1
t
AD
t
AD
t
CSD
t
RWD
t
RSD
t
RSD
t
RDS
t t
BSD BSD
t t
DACD DACD
t
DACD
t
DACD

Figure 22.19 Burst ROM Bus Cycle (No Wait)

TB2 TB1 TB2
t
RDH
Rev. 6.0, 07/02, page 881 of 986
TB1 T2
t
AD
t
CSD
t
RWD
t
RSD
t t
RDS RDH
t
DACD