Hitachi SH7750 Hardware Manual page 43

Figure 21.3 H-UDI Reset .................................................................................................... 811
Figure 22.1 EXTAL Clock Input Timing............................................................................ 862
Figure 22.2(1) CKIO Clock Output Timing ............................................................................ 862
Figure 22.2(2) CKIO Clock Output Timing ............................................................................ 862
Figure 22.3 Power-On Oscillation Settling Time................................................................ 863
Standby Return Oscillation Settling Time (Return by RESET)....................... 863
Figure 22.4
Figure 22.5 Power-On Oscillation Settling Time................................................................ 864
Standby Return Oscillation Settling Time (Return by RESET)....................... 864
Figure 22.6
Figure 22.7 Standby Return Oscillation Settling Time (Return by NMI) ........................... 865
Standby Return Oscillation Settling Time (Return by IRL3-IRL0) ................ 865
Figure 22.8
PLL Synchronization Settling Time in Case of RESET or NMI Interrupt ...... 866
Figure 22.9
Figure 22.10 PLL Synchronization Settling Time in Case of IRL Interrupt ......................... 866
Figure 22.11 Manual Reset Input Timing ............................................................................. 867
Figure 22.12 Mode Input Timing .......................................................................................... 867
Figure 22.13 Control Signal Timing ..................................................................................... 870
Figure 22.14 Pin Drive Timing for Standby Mode ............................................................... 870
Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait) ............................................... 877
Figure 22.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) ................................ 878
Figure 22.17 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)879
Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time
Insertion, AnS = 1, AnH = 1)........................................................................... 880
Figure 22.19 Burst ROM Bus Cycle (No Wait) .................................................................... 881
Figure 22.20 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait;
2nd/3rd/4th Data: One Internal Wait) .............................................................. 882
Figure 22.21 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion,
AnS = 1, AnH = 1)........................................................................................... 883
Figure 22.22 Burst ROM Bus Cycle (One Internal Wait + One External Wait) ................... 884
Figure 22.23 Synchronous DRAM Auto-Precharge Read Bus Cycle:
Single (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011)........................... 885
Figure 22.24 Synchronous DRAM Auto-Precharge Read Bus Cycle:
Burst (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) ............................ 886
Figure 22.25 Synchronous DRAM Normal Read Bus Cycle:
ACT + READ Commands, Burst (RCD[1:0] = 01, CAS Latency = 3) ........... 887
Figure 22.26 Synchronous DRAM Normal Read Bus Cycle:
PRE + ACT + READ Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001,
CAS Latency = 3) ............................................................................................ 888
Figure 22.27 Synchronous DRAM Normal Read Bus Cycle:
READ Command, Burst (CAS Latency = 3) ................................................... 889
Figure 22.28 Synchronous DRAM Auto-Precharge Write Bus Cycle:
Single (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) ......................... 890
Figure 22.29 Synchronous DRAM Auto-Precharge Write Bus Cycle:
Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)........................... 891
Rev. 6.0, 07/02, page xliii of I