Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment
Operation
Access
Size
Address No. D31–D24 D23–D16 D15–D8 D7–D0
Byte
2n
1
2n+1
1
Word
2n
1
Long-
4n
1
word
4n+2
2
Quad-
8n
1
word
8n+2
2
8n+4
3
8n+6
4
Rev. 6.0, 07/02, page 380 of 986
Data Bus
—
—
—
—
—
Data
7–0
—
—
Data
15–8
—
—
Data
15–8
—
—
Data
31–24
—
—
Data
15–8
—
—
Data
31–24
—
—
Data
47–40
—
—
Data
63–56
WE3,
WE3
WE2,
WE2
WE3
WE3
WE2
WE2
CAS3
CAS3
CAS3
CAS3,
CAS2
CAS2,
CAS2
CAS2
DQM3
DQM2
Data
7–0
—
Data
7–0
Data
7–0
Data
23–16
Data
7–0
Data
23–16
Data
39–32
Data
55–48
Strobe Signals
WE1,
WE1
WE0,
WE0
WE1
WE1
WE0
WE0
CAS1
CAS1,
CAS1
CAS1
CAS0
CAS0,
CAS0
CAS0
DQM1
DQM0
Asserted
Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted