Hitachi SH7750 Hardware Manual page 507

Tm1 Tmd1w Tmd1
CKIO
/
D63–D0
A D0
RD/
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.57 MPX Interface Timing 1
(Single Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits)
Rev. 6.0, 07/02, page 457 of 986