Figure 22.60 Memory Byte Control Sram Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, Ans[0] = 1, Anh[1:0] =01) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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Notes: IO: DACK device

SA: Single address DMA transfer

DA: Dual address DMA transfer

DACK set to active-high

Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address

Setup/Hold Time Insertion, AnS[0] = 1, AnH[1:0] =0 1)

(SA: IO ← memory)

Rev. 6.0, 07/02, page 923 of 986

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