Figure 23.58 Memory Byte Control Sram Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, Ans [0] = 1, Anh [1:0] = 01) - Hitachi SH7751 Hardware Manual

Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.58 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address
Setup/Hold Time Insertion, AnS [0] = 1, AnH [1:0] = 01)
Rev. 3.0, 04/02, page 1014 of 1064
TS1
CKIO
t
AD
A25–A0
t
CSD
t
RWD
RD/
t
RSD
D31–D0
(read)
t
WED1
t
BSD
t
DACD
DACKn
(SA: IO ← memory)
t
DACD
DACKn
(DA)
T1 T2 TH1
t
RSD
t t
RDS RDH
t
WEDF
t
BSD
t
DACD
t
AD
t
CSD
t
RWD
t
RSD
t
WED1
t
DACD