Hitachi SH7751 Hardware Manual page 777

Table 19.4 Interrupt Exception Handling Sources and Priority Order (cont)
Interrupt Source
PCIC (0) PCISERR
PCIC (1) PCIERR
PCIPWDWN
PCIPWON
PCIDMA0
PCIDMA1
PCIDMA2
PCIDMA3
TMU3 TUNI3
TMU4 TUNI4
TMU0 TUNI0
TMU1 TUNI1
TMU2 TUNI2
TICPI2
RTC ATI
PRI
CUI
SCI ERI
RXI
TXI
TEI
SCIF ERI
RXI
BRI
TXI
WDT ITI
REF RCMI
ROVI
Notes: * SH7751R only
TUNI0–TUNI4: Underflow interrupts
TICPI2: Input capture interrupt
Rev. 3.0, 04/02, page 738 of 1064
INTEVT Interrupt Priority
Code (Initial Value)
H'A00 15–0 (0)
H'AE0 15–0 (0)
H'AC0
H'AA0
H'A80
H'A60
H'A40
H'A20
H'B00 15–0 (0)
H'B80 15–0 (0)
H'400 15–0 (0)
H'420 15–0 (0)
H'440 15–0 (0)
H'460
H'480 15–0 (0)
H'4A0
H'4C0
H'4E0 15–0 (0)
H'500
H'520
H'540
H'700 15–0 (0)
H'720
H'740
H'760
H'560 15–0 (0)
H'580 15–0 (0)
H'5A0
IPR (Bit Priority within
Numbers) IPR Setting Unit
INTPRI00 —
(3–0)
INTPRI00 High
(7–4) 









Low
INTPRI00 —
(11–8)
INTPRI00 —
(15–12)
IPRA (15–12) —
IPRA (11–8) —
IPRA (7–4) High
Low
IPRA (3–0) High



Low
IPRB (7–4) High




Low
IPRC (7–4) High




Low
IPRB (15–12) —
IPRB (11–8) High
Low
Default
Priority
High






























































Low