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22.3.11 PCI Bus Basic Interface
The PCI interface of this LSI conforms to the PCI version 2.1 stipulations and can be connected to
a device with a PCI bus interface.
While the PCIC is set in host mode, or while set in non-host mode, operation differs according to
whether or not bus parking is performed, and whether or not the PCI bus arbiter function is
enabled or not.
In host mode, the AD, PAR, C/
being performed on the PCI bus (bus parking). When the PCIC subsequently starts transfers as
master, these signal lines continue to be driven until the end of the address phase. However, in
non-host mode, the master performing parking is determined according to the GNT output by the
external arbiter. When the master performing parking is not the same master as that starting the
subsequent transfer, a high impedance state of at least one clock is generated prior to the address
phase.
In host mode, the arbiters in the PCICs and the REQ and GNT between PCICs are connected
internally. Here, pins
function as the REQ inputs from the external masters 1 to 4. Similarly,
,
Including the PCIC, arbitration of up to five masters is possible.
In non-host mode, pins
/
Master Read/Write Cycle Timing: Figures 22.7 is an example of a single-write cycle in host
mode. Figure 22.8 is an example of a single read cycle in host mode. Figure 22.9 is an example of
a burst write cycle in non-host mode. And Figure 22.10 is an example of a burst read cycle in non-
host mode. Note that the response speed of
connected target device.
In PIO transfers, always use single read/write cycles.
The issuing of configuration transfers is only possible in host mode.
LOCK transfers are possible only using PIO transfers.
Rev. 3.0, 04/02, page 898 of 1064
signal lines are driven by the PCIC when transfers are not
,
/
, and
function as the GNT outputs to external masters 1 to 4.
/
functions as the REQ output of the PCIC.
/MD9,
functions as the GNT input of the PCIC, while
and
/MD10, and
/
differs according to the
,
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