Table 23.27 Bus Timing (2) - Hitachi SH7751 Hardware Manual

Superh risc engine
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Table 23.27 Bus Timing (2)

Item
Address delay time

delay time

delay time

delay time

delay time
Read data setup time
Read data hold time

delay time (falling
edge)

delay time
Write data delay time

setup time

hold time

delay time

delay time 1

delay time 2
CKE delay time
DQM delay time

delay time

setup time

hold time
  
delay time
(falling edge)
 
delay time
DACK delay time
DACK delay time
(falling edge)
Rev. 3.0, 04/02, page 966 of 1064
HD6417751VF133
*1
Symbol
Min
t
1.0
AD
t
1.0
BSD
t
1.0
CSD
t
1.0
RWD
t
1.0
RSD
t
3.5
RDS
t
1.5
RDH
t
1.0
WEDF
t
1.0
WED1
t
1.0
WDD
t
3.5
RDYS
t
1.5
RDYH
t
1.0
RASD
t
1.0
CASD1
t
1.0
CASD2
t
1.0
CKED
t
1.0
DQMD
t
1.0
FMD
t
3.5
IO16S
t
1.5
IO16H
t
1.0
ICWSDF
t
1.0
ICRSD
t
1.0
DACD
t
1.0
DACDF
HD6417751BP167
HD6417751BP167I
HD6417751F167
HD6417751F167I
*2
Max
Min
8
1.0
8
1.0
8
1.0
8
1.0
8
1.0
3.5
1.5
8
1.0
8
1.0
8
1.0
3.5
1.5
8
1.0
8
1.0
8
1.0
8
1.0
8
1.0
8
1.0
3.5
1.5
8
1.0
8
1.0
8
1.0
8
1.0
Max
Unit
Notes
8
ns
8
ns
8
ns
8
ns
8
ns
ns
ns
8
ns
Relative to
CKIO falling
edge
8
ns
8
ns
ns
ns
8
ns
8
ns
DRAM
8
ns
SDRAM
8
ns
SDRAM
8
ns
SDRAM
8
ns
MPX
ns
PCMCIA
ns
PCMCIA
8
ns
PCMCIA
8
ns
PCMCIA
8
ns
8
ns
Relative to
CKIO falling
edge

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