Figure 22.21(1) Data Alignment At Target Memory Transfer (Big-Endian Local Bus) - Hitachi SH7751 Hardware Manual

Target memory read transfers (local bus → PCI bus) when local bus is big endian
Size
31
LW
B0 B1 B2 B3
Target memory write transfers (local bus ← PCI bus) when local bus is big endian
Size
31
B
B0
B
B
B
W B0 B1
W
B + B
B0
B + B
B + B
B0
B + B
W + B B0 B1
W + B B0 B1
B + W
B0
B + W
—
LW
B0 B1 B2 B3

Figure 22.21(1) Data Alignment at Target Memory Transfer (Big-Endian Local Bus)

Local bus
0
Local bus
0
B1
B2
B3
B2 B3
+
B1 +
+
B1 +
+
+
+
B1 +
—
PCI bus
31
B3 B2 B1 B0
PCI bus
31
B2
B3
B3 B2
B2 B2
B3 B3
B3 B3
B2 B2 B1
B2 B2 B1 B0
B3 B3
B2 B3 B3 B2
B2 B3 B3 B2 B1
B3 B2 B1 B0
Rev. 3.0, 04/02, page 915 of 1064
BE
0
H'0 to H'F
BE
0
1110
B0
1101
B1
1011
0111
B1 B0 1100
0011
1010
B0
0101
B1
0110
B0
1001
1000
B1 B0 0100
0010
B0
0001
1111
0000