Figure 14.55 Single Address Mode/Burst Mode/External Bus  External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer; Table 14.19 Dmac Interrupt-Request Codes - Hitachi SH7751 Hardware Manual

CKIO
/
A25–A0
D63–D0
RAS,
CAS, WE
ID1, ID0
Figure 14.55 Single Address Mode/Burst Mode/External Bus
Block Transfer/Channel 0 On-Demand Data Transfer

Table 14.19 DMAC Interrupt-Request Codes

Source of the Interrupt
DMTE0
DMTE1
DMTE2
DMTE3
DMTE4
DMTE5
DMTE6
DMTE7
DMAE
DMTE4–DMTE7: These codes are not used in the SH7751.
DTR
Description
CH0 transfer-end interrupt
CH1 transfer-end interrupt
CH2 transfer-end interrupt
CH3 transfer-end interrupt
CH4 transfer-end interrupt
CH5 transfer-end interrupt
CH6 transfer-end interrupt
CH7 transfer-end interrupt
Address error interrupt
RA CA
BA
RD
 
External Device 32-Byte
INTEVT Code
H'640
H'660
H'680
H'6A0
H'780
H'7A0
H'7C0
H'7E0
H'6C0
Rev. 3.0, 04/02, page 565 of 1064
D2
D0 D1
00
Priority
High
Low