Register Configuration; Table 13.2 Bsc Registers - Hitachi SH7751 Hardware Manual


Notes: *1 MD3/
when BCR1.A56PCM = 1.


*2 MD4/
when BCR1.A56PCM = 1.
13.1.4

Register Configuration

The BSC has the 11 registers shown in table 13.2. In addition, the synchronous DRAM mode
register incorporated in synchronous DRAM can also be accessed as an SH7751 Series register.
The functions of these registers include control of interfaces to various types of memory, wait
states, and refreshing.

Table 13.2 BSC Registers

Name
Bus control register 1
Bus control register 2
Bus control register 3*
Bus control register 4*
Wait state control
register 1
Wait state control
register 2
Wait state control
register 3
Memory control register MCR
PCMCIA control register PCR
Refresh timer
control/status register
Refresh timer counter
Refresh time constant
counter
Refresh count register
Synchronous For
DRAM mode area 2
registers
For
area 3
Notes: *1 For details, see section 13.2.10, Synchronous DRAM Mode Register (SDMR).
*2 SH7751R only
Rev. 3.0, 04/02, page 310 of 1064
input/output switching is performed by BCR1.A56PCM. Output is selected
input/output switching is performed by BCR1.A56PCM. Output is selected
Abbrevia- R/W
tion
BCR1 R/W
BCR2 R/W
2
BCR3 R/W
2
BCR4 R/W
WCR1 R/W
WCR2 R/W
WCR3 R/W
R/W
R/W
RTCSR R/W
RTCNT R/W
RTCOR R/W
RFCR R/W
SDMR2 W
SDMR3
Initial P4
Value Address
H'0000 0000 H'FF80 0000 H'1F80 0000 32
H'3FFC H'FF80 0004 H'1F80 0004 16
H'0000 H'FF80 0050 H'1F80 0050 16
H'0000 0000 H'FE0A 00F0 H'1E0A 00F0 32
H'7777 7777 H'FF80 0008 H'1F80 0008 32
H'FFFE EFFF H'FF80 000C H'1F80 000C 32
H'0777 7777 H'FF80 0010 H'1F80 0010 32
H'0000 0000 H'FF80 0014 H'1F80 0014 32
H'0000 H'FF80 0018 H'1F80 0018 16
H'0000 H'FF80 001C H'1F80 001C 16
H'0000 H'FF80 0020 H'1F80 0020 16
H'0000 H'FF80 0024 H'1F80 0024 16
H'0000 H'FF80 0028 H'1F80 0028 16
— H'FF90 xxxx*
H'FF94 xxxx*
Area 7 Access
Address Size
1
H'1F90 xxxx 8
1
H'1F94 xxxx