Hitachi SH7751 Hardware Manual page 32

Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS [2:0] = 001, TRC [2:0] = 001) ............................................................. 1004
Figure 23.49 DRAM Bus Cycle: DRAM Self-Refresh (TRC [2:0] = 001)........................... 1005
Figure 23.50 PCMCIA Memory Bus Cycle
(1) TED [2:0] = 000, TEH [2:0] = 000, No Wait
(2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External
Wait.................................................................................................................. 1006
Figure 23.51 PCMCIA I/O Bus Cycle
(1) TED [2:0] = 000, TEH [2:0] = 000, No Wait
(2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External
Wait.................................................................................................................. 1007
Figure 23.52 PCMCIA I/O Bus Cycle
(TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait, Bus Sizing).............. 1008
Figure 23.53 MPX Basic Bus Cycle: Read
(1) 1st Data (One Internal Wait)
(2) 1st Data (One Internal Wait + One External Wait) .................................... 1009
Figure 23.54 MPX Basic Bus Cycle: Write
(1) 1st Data (No Wait)
(2) 1st Data (One Internal Wait)
(3) 1st Data (One Internal Wait + One External Wait) .................................... 1010
Figure 23.55 MPX Bus Cycle: Burst Read
(1) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait)
(2) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait + One
External Wait).................................................................................................. 1011
Figure 23.56 MPX Bus Cycle: Burst Write
(1) No Internal Wait
(2) 1st Data (One Internal Wait), 2nd to 8th Data (No Internal Wait + External
Wait Control) ................................................................................................... 1012
Figure 23.57 Memory Byte Control SRAM Bus Cycles
(1) Basic Read Cycle (No Wait)
(2) Basic Read Cycle (One Internal Wait)
(3) Basic Read Cycle (One Internal Wait + One External Wait) ..................... 1013
Figure 23.58 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait,
Address Setup/Hold Time Insertion, AnS [0] = 1, AnH [1:0] = 01) ................ 1014
Figure 23.59 TCLK Input Timing......................................................................................... 1019
Figure 23.60 RTC Oscillation Settling Time at Power-On ................................................... 1019
Figure 23.61 SCK Input Clock Timing ................................................................................. 1019
Figure 23.62 SCI I/O Synchronous Mode Clock Timing...................................................... 1019
Figure 23.63 I/O Port Input/Output Timing .......................................................................... 1020


Figure 23.64(a)


Figure 23.64(b)
Figure 23.65 TCK Input Timing ........................................................................................... 1021
 
Figure 23.66
/DRAK Timing ..................................................................................... 1020

/ Input Timing and
Hold Timing........................................................................................ 1021

Output Timing .................................... 1020
Rev. 3.0, 04/02, page xxxi of xxxviii