Hitachi SH7751 Hardware Manual page 37

Table 21.3 Structure of Boundary Scan Register ................................................................. 784
Table 22.1 Pin Configuration ............................................................................................... 804
Table 22.2 List of PCI Configuration Registers ................................................................... 806
Table 22.3 PCI Configuration Register Configuration......................................................... 807
Table 22.4 List of PCIC Local Registers.............................................................................. 808
Table 22.5 List of CLASS23 to 16 Base Class Codes (CLASS23 to 16)............................. 818
Table 22.6 Memory Space Base Address Register (BASE0)............................................... 824
Table 22.7 Memory Space Base Address Register (BASE1)............................................... 826
Table 22.8 Operating Modes ................................................................................................ 879
Table 22.9 PCI Command Support ...................................................................................... 880
Table 22.10 Access Size......................................................................................................... 911
Table 22.11 DMA Transfer Access Size and Endian Conversion Mode ............................... 913
Table 22.12 Target Transfer Access Size and Endian Conversion Mode .............................. 914
Table 22.13 Interrupts ............................................................................................................ 920
Table 22.14 Method of Stopping Clock per Operating Mode ................................................ 925
Table 23.1 Absolute Maximum Ratings............................................................................... 929
Table 23.2 DC Characteristics (HD6417751RBP240)......................................................... 930
Table 23.3 DC Characteristics (HD6417751RF240) ........................................................... 932
Table 23.4 DC Characteristics (HD6417751RBP200)......................................................... 934
Table 23.5 DC Characteristics (HD6417751RF200) ........................................................... 936
Table 23.6 DC Characteristics (HD6417751BP167) ........................................................... 938
Table 23.7 DC Characteristics (HD6417751BP167I) .......................................................... 940
Table 23.8 DC Characteristics (HD6417751F167) .............................................................. 942
Table 23.9 DC Characteristics (HD6417751F167I)............................................................. 944
Table 23.10 DC Characteristics (HD6417751VF133) ........................................................... 946
Table 23.11 Permissible Output Currents .............................................................................. 948
Table 23.12 Clock Timing (HD6417751RBP240)................................................................. 948
Table 23.13 Clock Timing (HD6417751RF240) ................................................................... 948
Table 23.14 Clock Timing (HD6417751RBP200)................................................................. 949
Table 23.15 Clock Timing (HD6417751RF200) ................................................................... 949
Table 23.16 Clock Timing (HD6417751BP167(I), HD6417751F167(I)).............................. 949
Table 23.17 Clock Timing (HD6417751VF133) ................................................................... 949
Table 23.18 Clock and Control Signal Timing (HD6417751RBP240).................................. 950
Table 23.19 Clock and Control Signal Timing (HD6417751RF240) .................................... 951
Table 23.20 Clock and Control Signal Timing (HD6417751RBP200).................................. 952
Table 23.21 Clock and Control Signal Timing (HD6417751RF200) .................................... 953
Table 23.22 Clock and Control Signal Timing (HD6417751BP167, HD6417751F167,
HD6417751BP167I, HD6417751F167I) ........................................................... 954
Table 23.23 Clock and Control Signal Timing (HD6417751VF133) .................................... 955
Table 23.24 Control Signal Timing (1) .................................................................................. 961
Table 23.25 Control Signal Timing (2) .................................................................................. 962
Table 23.26 Bus Timing (1) ................................................................................................... 964
Table 23.27 Bus Timing (2) ................................................................................................... 966
Rev. 3.0, 04/02, page xxxvi of xxxviii