Instruction Set; Table 7.2 Notation Used In Instruction List - Hitachi SH7751 Hardware Manual

7.3

Instruction Set

Table 7.2 shows the notation used in the following SH instruction list.
Table 7.2 Notation Used in Instruction List
Item Format
Instruction OP.Sz SRC, DEST
mnemonic
Summary of
operation
Instruction code MSB
Privileged mode
T bit Value of T bit after
instruction execution
 
Note: Scaling ( 1,
Description
OP:
Sz:
SRC:
DEST:


(xx):
M/Q/T:
&:
|:


~:
<<n, >>n: n-bit shift

LSB mmmm: Register number (Rm, FRm)
nnnn:
0000:
0001:
1111:
mmm:
nnn:
000:
001:
111:
mm:
nn:
00:
01:
10:
11:
iiii:
dddd:
"Privileged" means the instruction can only be executed
in privileged mode.
—: No change
 
2, 4, or 8) is executed according to the size of the instruction operand(s).
Operation code
Size
Source
Source and/or destination operand

, : Transfer direction
Memory operand
SR flag bits
Logical AND of individual bits
Logical OR of individual bits
: Logical exclusive-OR of individual bits
Logical NOT of individual bits
Register number (Rn, FRn)
R0, FR0
R1, FR1
:
R15, FR15
Register number (DRm, XDm, Rm_BANK)
Register number (DRm, XDm, Rn_BANK)
DR0, XD0, R0_BANK
DR2, XD2, R1_BANK
:
DR14, XD14, R7_BANK
Register number (FVm)
Register number (FVn)
FV0
FV4
FV8
FV12
Immediate data
Displacement
Rev. 3.0, 04/02, page 173 of 1064