Hitachi SH7751 Hardware Manual page 388

For Synchronous DRAM Interface:
AMX AMXEXT
0 0
1
1 0
1
2 —
3 —
4 —
5 —
6 0
1
7 —
Note: a[x]: External address, not address pin
Bit 2—Refresh Control (RFSH): Specifies refresh control. Selects whether refreshing is
performed for DRAM and synchronous DRAM. When the refresh function is not used, the refresh
request cycle generation timer can be used as an interval timer.
Bit 2: RFSH
0
1
Bit 1—Refresh Mode (RMODE): Specifies whether normal refreshing or self-refreshing is
performed when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is cleared to 0, CAS-
before-RAS refreshing or auto-refreshing is performed for DRAM and synchronous DRAM, using
the cycle set by refresh-related registers RTCNT, RTCOR, and RTCSR. If a refresh request is
issued during an external bus cycle, the refresh cycle is executed when the bus cycle ends. When
the RFSH bit is 1 and this bit is set to 1, the self-refresh state is set for DRAM and synchronous
DRAM, after waiting for the end of any currently executing external bus cycle. All refresh
requests for memory in the self-refresh state are ignored.
Bit 1: RMODE
0
1
SZ
32
Description
Refreshing is not performed
Refreshing is performed
Description
CAS-before-RAS refreshing is performed (when RFSH = 1)
Self-refreshing is performed (when RFSH = 1)
Example Synchronous DRAM
Configurations

(16M: 512k 16 bits

(16M: 512k 16 bits
 
(16M: 1M 8 bits 2)
 
(16M: 1M 8 bits 2)
 
(64M: 1M 16 bits
 
(64M: 2M 8 bits 4)

(64M: 512k 32 bits
 
(64M: 1M 32 bits
 
(64M: 4M 4 bits 4)
 
(256M: 4M 16 bits

(16M: 256k 32 bits
Rev. 3.0, 04/02, page 349 of 1064
BANK
 
2) 2 a[21]*
 
2) 2 a[20]*

4 a[22]*

4 a[21]*

4) 2 a[23:22]*

4 a[24:23]*
 
4) 1 a[22:21]*

2) 1 a[22]*

8 a[25:24]*

4) 2 a[25:24]*
 
2) 1 a[20]*
(Initial value)
(Initial value)