Figure 4.3 Configuration Of Operand Cache (Sh7751R) - Hitachi SH7751 Hardware Manual

Effective address
31 26 25
OIX
ORA
Entry
selection
22
9
0
MMU
19
511
Compare
way-0

Figure 4.3 Configuration of Operand Cache (SH7751R)

Tag
Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is
not initialized by a power-on or manual reset.


V bit (validity bit)
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
RAM area
determination
[13]
Address array
(way 0, way 1)
Tag U V
19 bits 1 bit 1 bit
Compare
way-1
Hit signal
13 12 10
[12:5]
Data array (way 0, way 1)
3
LW0 LW1 LW2 LW3
32 bits 32 bits 32 bits 32 bits
Read data
Rev. 3.0, 04/02, page 93 of 1064
5 4 2 0
Longword (LW)
selection
LW4 LW5 LW6 LW7
32 bits 32 bits 32 bits 32 bits
Write data
LRU
1 bit