Hitachi SH7751 Hardware Manual page 543

In figure 14.22, with a 32-byte data size, 32-bit bus width, and SDRAM: row hit write, DMAC
transfer begins, at the earliest, six CKIO cycles after the first sampling operation. The second
sampling operation begins one cycle after DACK is asserted for the first DMAC transfer.
4. Burst Mode, Dual Address Mode, Edge Detection
In burst mode using dual address mode and edge detection,
the first cycle only.
For example, in the case shown in figure 14.15, DMAC transfer begins, at the earliest, five
CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of
the number of data transfers set in DMATCR.
therefore DRAK is output in the first cycle only.
In the case of dual address mode transfer initiated by an external request, the DACK signal can
be output in either the read cycle or the write cycle of the DMAC transfer according to the
specification of the AM bit in CHCR.
5. Burst Mode, Single Address Mode, Edge Detection
In burst mode using single address mode and edge detection,
only in the first cycle.
For example, in the case shown in figure 14.21, DMAC transfer begins, at the earliest, five
cycles after the first sampling operation. DMAC transfer then continues until the end of the
number of data transfers set in DMATCR.
therefore DRAK is output in the first cycle only.
In single address mode, the DACK signal is output every DMAC transfer cycle.
Suspension of DMA Transfer in Case of


With level detection in burst mode or cycle steal mode, and in dual address mode or single
address mode, the external device for which DMA transfer is being executed can judge from the
rising edge of CKIO that DRAK has been asserted, and can suspend DMA transfer by negating


. In this case, the next DRAK signal is not output.
Rev. 3.0, 04/02, page 504 of 1064




is not sampled during this time, and


is not sampled during this time, and




Level Detection
sampling is performed in


sampling is performed