Figure 13.63 Mpx Interface Timing - Hitachi SH7751 Hardware Manual

CKIO
/
D31–D0
RD/
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
(Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits,
Rev. 3.0, 04/02, page 446 of 1064
Tm1 Tmd1w
A

Figure 13.63 MPX Interface Timing 4

Transfer Data Size: 64 Bits)
Tmd1w Tmd1
D0
Tmd2
D1