Figure 13.33 Burst Write Timing (Different Row Addresses) - Hitachi SH7751 Hardware Manual

Figure 13.33 Burst Write Timing (Different Row Addresses)

Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between
an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the
DMAC, to provide faster access to synchronous DRAM. As synchronous DRAM is internally
divided into two or four banks, after a READ or WRIT command is issued for one bank it is
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