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31
PCI I/O space
H'FE24–H'FE27
address
31
PIOIOBR
PIO Transfer Error: An error on the PCI bus that occurs in a transfer during a PIO write
operation is not detected. When an error is generated during a PIO read operation, the PIO transfer
is forcibly terminated to prevent effects on the DMA transfer and target transfer. However,
accuracy of the read data is not guaranteed.
22.3.8
Target Transfers
The following commands are available for transferring data in target transfers.
Memory read and memory write
I/O read and I/O write (access to PCIC local registers)
Configuration read, configuration write
Locked transfer is supported.
High-speed back-to-back, is not supported.
When the PCIC is operating in non-host mode, no response is made on reception of special cycle
commands.
Memory Read/Memory Write Commands: In the case of memory read and memory write
commands, both single transfers and burst transfers are supported on the PCI bus. Data on the PCI
bus is always longword data, but
memory read, longword data is always read from the local bus and output to the PCI bus. In the
case of memory write, the internal control allows only the writing of valid byte lane data to the
Rev. 3.0, 04/02, page 888 of 1064
H'FE200000
PCI register space
H'FE23FFFF
H'FE240000
PIC I/O space
H'FE27FFFF
18 17
0
18 17
0
LOCK identifier
Figure 22.3 PIO I/O Space Access
can be used to control the valid byte lane. In the case of
256 kbytes
256 kbytes
31
PCI address
18 17
0
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