Hitachi SH7751 Hardware Manual page 902

Bits 10 and 9—Alignment Mode (ALNMD): Sets data alignment when local bus is big endian
Bit 10: ALNMD10
0
1
Notes: W: Word
LW: Longword
For details, refer to section 22.4, Endians.
Bit 8—DMA Transfer End Status (DMAST): Indicates the DMA transfer end status.
Bit 8: DMAST
0
1
Bit 7—DMA Transfer Termination Interrupt Mask (DMAIM): Specifies the DMA transfer
termination interrupt mask.
Bit 7: DMAIM
0
1
Bit 6—DMA Transfer Termination Interrupt Status (DMAIS): Indicates the DMA transfer
termination interrupt status. The interrupt status is set even when the interrupt mask is set.
Bit 6: DMAIS
When writing
When reading
Bit 5—Local Address Control (LAHOLD): Local address control during DMA transfer
Bit 5: LAHOLD
0
1
Bit 9: ALNMD9
0
1
0
1
Description
Normal termination
Abnormal termination (Error detection or forced DMA transfer termination)
Description
Interrupt disabled
Interrupt enabled
0
1
0
1
Description
Incremented
High address fixed (Address A[4:0] is incremented)
Description
Byte boundary mode
W/LW boundary mode 1 (LW data is sent as byte
W/LW boundary mode 2 (LW data is sent as word
W/LW boundary mode 3 (LW data is sent as longword)
Description
Ignored
Status clear
Interrupt not detected
Interrupt detected
Rev. 3.0, 04/02, page 863 of 1064
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