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from both the PP bus and PCI bus. When set to 0, the respective interrupt is disabled, and enabled
when set to 1.
The PCIINTM register is initialized to H'00000000 at a power-on reset and software reset.
Bits 31 to 16—Reserved: These bits always return 0 when read. Always write 0 to these bits.
Bit 15—Unlocked Transfer Detection Interrupt Mask (M_LOCKON)
Bit 14—Target Target Abort Interrupt Mask (T_TGT_ABORT)
Bits 13 to 10—Reserved: These bits always return 0 when read. Always write 0 to these bits.
Bit 9—Target Retry Timeout Interrupt Mask (TGT_RETRY)
Bit 8—Master Function Disable Error Interrupt Mask (MST_DIS)
Bit 7—Address Parity Error Detection Interrupt Mask (ADRPERR)
Bit 6—
Detection Interrupt Mask (SERR_DET)
Bit 5—Target Write Data Parity Error Interrupt Mask (T_DPERR_WT)
Bit 4—Target Read
Detection Interrupt Mask (T_PERR_DET)
Bit 3—Master Target Abort Interrupt Mask (M_TGT_ABORT)
Bit 2—Master Master Abort Interrupt Mask (M_MST_ABORT)
Bit 1—Master Write Data Parity Error Interrupt Mask (M_DPERR_WT)
Bit 0—Master Read Data Parity Error Interrupt Mask (M_DPERR_RD)
Rev. 3.0, 04/02, page 849 of 1064
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