Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.14 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)
T1
CKIO
t
AD
A25 – A0
t
CSD
t
RWD
RD/
t
RSD
D31 – D0
(read)
t
WED1
t
WDD
D31 – D0
(write)
t
BSD
t
DACD
DACKn
(SA: IO ← memory)
t
DACDF
DACKn
(SA: IO → memory)
t
DACD
DACKn
(DA)
Tw
T2
t
RSD
t
RDS
t
t
WEDF
WEDF
t
t
WDD
WDD
t
BSD
t
t
RDYS
RDYH
t
DACD
t
DACDF
t
DACD
Rev. 3.0, 04/02, page 969 of 1064
t
AD
t
CSD
t
RWD
t
RSD
t
RDH
t
DACD