Table 23.29 Peripheral Module Signal Timing (2) - Hitachi SH7751 Hardware Manual

Table 23.29 Peripheral Module Signal Timing (2)

Module Item
TMU, Timer clock pulse
RTC width (high)
Timer clock pulse
width (low)
Timer clock rise
time
Timer clock fall
time
Oscillation
settling time
SCI Input clock cycle
(asynchronous)
Input clock cycle
(synchronous)
Input clock pulse
width
Input clock rise
time
Input clock fall
time
Transfer data
delay time
Receive data
setup time
(synchronous)
Receive data
hold time
(synchronous)
I/O Output data
ports delay time
Input data setup
time
Input data hold
time
HD6417751VF133
*2
Symbol Min Max
t 4 —
TCLKWH
t 4 —
TCLKWL
t — 0.8
TCLKr
t — 0.8
TCLKf
t — 3
ROSC
t 4 —
Scyc
t 6 —
Scyc
t 0.4 0.6
SCKW
t — 0.8
SCKr
t — 0.8
SCKf
t — 30
TXD
t 0.8 —
RXS
t 0.8 —
RXH
t — 8
PORTD
t 3.5 —
PORTS
t 1.5 —
PORTH
HD6417751BP167
HD6417751BP167I
HD6417751F167
HD6417751F167I
*3
Min Max Unit
4 — Pcyc*
4 — Pcyc*
— 0.8 Pcyc*
— 0.8 Pcyc*
— 3 s
4 — Pcyc*
6 — Pcyc*
0.4 0.6 t
Scyc
— 0.8 Pcyc*
— 0.8 Pcyc*
— 30 ns
0.8 — Pcyc*
0.8 — Pcyc*
— 8 ns
3.5 — ns
1.5 — ns
Rev. 3.0, 04/02, page 1017 of 1064
Figure Notes
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