Peripheral Module Signal Timing - Hitachi SH7750 series Hardware Manual

23.3.4

Peripheral Module Signal Timing

Table 23.17 Peripheral Module Signal Timing
Module Item
TMU, Timer clock
RTC pulse width
(high)
Timer clock
pulse width
(low)
Timer clock
rise time
Timer clock
fall time
Oscillation
settling time
SCI Input clock
cycle (asyn-
chronous)
Input clock
cycle (syn-
chronous)
Input clock
pulse width
Input clock
rise time
Input clock
fall time
Transfer data
delay time
Receive data
setup time
(synchronous)
Receive data
hold time
(synchronous)
Rev. 4.0, 04/00, page 806 of 850
HD6417750
VF128
2
64 MHz*
Symbol Min Max
t 4 —
TCLKWH
t 4 —
TCLKWL
t — 0.8
TCLKr
t — 0.8
TCLKf
t — 3
ROSC
t 4 —
Scyc
t 6 —
Scyc
t 0.4 0.6
SCKW
t — 0.8
SCKr
t — 0.8
SCKf
t — 30
TXD
t 16 —
RXS
t 16 —
RXH
HD6417750
F167
HD6417750
F167I
HD6417750 HD6417750
SVF133 SF167
3
67 MHz* 83 MHz*
Min Max Min
4 — 4
4 — 4
— 0.8 —
— 0.8 —
— 3 —
4 — 4
6 — 6
0.4 0.6 0.4
— 0.8 —
— 0.8 —
— 30 —
16 — 16
16 — 16
HD6417750
BP200M
HD6417750
SBP200
4 5
100 MHz*
Max Min Max
— 4 —
— 4 —
0.8 — 0.8
0.8 — 0.8
3 — 3
— 4 —
— 6 —
0.6 0.4 0.6
0.8 — 0.8
0.8 — 0.8
30 — 30
— 16 —
— 16 —
Unit Figure
1
Pcyc* 23.61
1
Pcyc* 23.61
1
Pcyc* 23.61
1
Pcyc* 23.61
S 23.62
1
Pcyc* 23.63
1
Pcyc* 23.63
t 23.63
Scyc
1
Pcyc* 23.63
1
Pcyc* 23.63
Ns 23.64
Ns 23.64
Ns 23.64