that in figure 13.31 or 13.34. In RAS down mode, too, a PRE command is issued before a refresh
cycle or before bus release due to bus arbitration.
CKIO
Bank
Precharge-sel
Address
RD/
DQMn
D63–D0
(read)
CKE
DACKn
(SA: IO ← memory)
Rev. 4.0, 04/00, page 360 of 850
Tr
Trw
Tc1
Tc2
Row
Row
Row
Figure 13.30 Burst Read Timing
Tc3 Tc4/Td1 Td2
H/L
c1
c1
Td3
Td4
c2
c3
c4