Hitachi SH7750 series Hardware Manual page 781

Tr
CKIO
t
AD
BANK
Precharge-sel
Addr
t
CSD
CSn
RD/WR
t
RASD
RAS
t
CASD2
CASS
DQMn
t
WDD
D63–D0
(write)
BS
CKE
t
DACD
DACKn
(SA: IO → memory)
Figure 23.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst
Trw Tc1
Row
t
AD
Row
H/L
Row c0
t
RWD
t
RASD
t t
CASD2 CASD2
t
DQMD
t
WDD
d0
t
BSD
(RCD = 1, TRWL = 2, TPC = 1)
Tc2 Tc3 Tc4
t
RWD
t
WDD
d1 d2 d3
t
BSD
t
DACD
Trwl Trwl Tpc
t
AD
t
CSD
t
DQMD
Rev. 4.0, 04/00, page 773 of 850