Table of Contents
Advertisement
21.1.3
Pin Configuration
Table 21.1 shows the H-UDI pin configuration.
Table 21.1 H-UDI Pins
Pin Name
Abbreviation
Clock pin
TCK
Mode pin
TMS
7567
Reset pin
Data input
TDI
pin
Data output
TDO
pin
Emulator pin $6(%5./
BRKACK
Notes: 1. Pulled up inside the chip. When designing a board that allows use of an emulator, or
when using interrupts and resets via the H-UDI, there is no problem in connecting a
pullup resistance externally.
2. When designing a board that enables the use of an emulator, or when using interrupts
and resets via the H-UDI, drive 7567 low for a period overlapping 5(6(7 at power-on,
and also provide for control by 7567 alone.
The maximum frequency of TCK (TMS, TDI, TDO) is 20 MHz. Make the TCK or SH7750 Series
CPG setting so that the TCK frequency is lower than that of the SH7750 Series' on-chip
peripheral module clock.
I/O
Function
Input
Same as the JTAG serial clock input
pin. Data is transferred from data
input pin TDI to the H-UDI circuit, and
data is read from data output pin
TDO, in synchronization with this
signal.
Input
The mode select input pin. Changing
this signal in synchronization with
TCK determines the meaning of the
data input from TDI. The protocol
conforms to the JTAG (IEEE Std
1149.1) specification.
Input
The input pin that resets the H-UDI.
This signal is received
asynchronously with respect to TCK,
and effects a reset of the JTAG
interface circuit when low. 7567 must
be driven low for a certain period
when powering on, regardless of
whether or not JTAG is used. This
differs from the IEEE specification.
Input
The data input pin. Data is sent to the
H-UDI circuit by changing this signal
in synchronization with TCK.
Output
The data output pin. Data is sent to
the H-UDI circuit by reading this
signal in synchronization with TCK.
Input/
Dedicated emulator pin
output
When Not Used
Open*
Open*
Fix at ground or
5(6(7*
Open*
Open
Open*
Rev. 4.0, 04/00, page 705 of 850
1
1
2
1
1
Advertisement
Table of Contents
