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Bits 2n + 1, 2n—Area n (1 to 6) Bus Width Specification (AnSZ1, AnSZ0): These bits specify
the bus width of area n (n = 1 to 6).
(Bit 0): PORTEN Bit 2n + 1: AnSZ1
0
0
1
1
0
1
Bit 1—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 0—Port Function Enable (PORTEN): Specifies whether pins D51 to D32 are used as a 20-
bit port. When this function is used, a bus width of 8, 16, or 32 bits should be set for all areas.
Bit 0: PORTEN
0
1
13.2.3
Wait Control Register 1 (WCR1)
Wait control register 1 (WCR1) is a 32-bit readable/writable register that specifies the number of
idle state insertion cycles for each area. With some kinds of memory, data bus drive does not go
off immediately after the read signal from off-chip goes off. As a result, there is a possibility of a
data bus collision when consecutive memory accesses are performed on memory in different
areas, or when a memory write is performed immediately after a read. In the SH7750 Series, the
number of idle cycles set in the WCR1 register are inserted automatically if there is a possibility of
this kind of data bus collision.
WCR1 is initialized to H'77777777 by a power-on reset, but is not initialized by a manual reset or
in standby mode.
Bit 2n: AnSZ0
0
1
0
1
0
1
0
1
Description
D51 to D32 are not used as a port
D51 to D32 are used as a port
Description
Bus width is 64 bits
Bus width is 8 bits
Bus width is 16 bits
Bus width is 32 bits
Reserved (Setting prohibited)
Bus width is 8 bits
Bus width is 16 bits
Bus width is 32 bits
Rev. 4.0, 04/00, page 281 of 850
(Initial value)
(Initial value)
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