Hitachi SH7750 series Hardware Manual page 13

14.1.4 Register Configuration......................................................................................... 423
14.2 Register Descriptions ........................................................................................................ 425
14.2.1 DMA Source Address Registers 0-3 (SAR0-SAR3) .......................................... 425
14.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3).................................. 426
14.2.3 DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3)......................... 427
14.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3)................................... 428
14.2.5 DMA Operation Register (DMAOR)................................................................... 436
14.3 Operation .......................................................................................................................... 439
14.3.1 DMA Transfer Procedure .................................................................................... 439
14.3.2 DMA Transfer Requests ...................................................................................... 441
14.3.3 Channel Priorities ................................................................................................ 444
14.3.4 Types of DMA Transfer....................................................................................... 447
14.3.5 Number of Bus Cycle States and '5(4 Pin Sampling Timing .......................... 456
14.3.6 Ending DMA Transfer ......................................................................................... 470
14.4 Examples of Use ............................................................................................................... 473
14.4.1 Examples of Transfer between External Memory and
an External Device with DACK........................................................................... 473
14.5 On-Demand Data Transfer Mode...................................................................................... 474
14.5.1 Operation ............................................................................................................. 474
14.5.2 Pins in DDT Mode............................................................................................... 476
14.5.3 Transfer Request Acceptance on Each Channel .................................................. 479
14.5.4 Notes on Use of DDT Module ............................................................................. 499
14.6 Usage Notes ...................................................................................................................... 502
Section 15 Serial Communication Interface (SCI)
15.1 Overview........................................................................................................................... 503
15.1.1 Features................................................................................................................ 503
15.1.2 Block Diagram..................................................................................................... 505
15.1.3 Pin Configuration................................................................................................. 506
15.1.4 Register Configuration......................................................................................... 506
15.2 Register Descriptions ........................................................................................................ 507
15.2.1 Receive Shift Register (SCRSR1)........................................................................ 507
15.2.2 Receive Data Register (SCRDR1) ....................................................................... 507
15.2.3 Transmit Shift Register (SCTSR1) ...................................................................... 508
15.2.4 Transmit Data Register (SCTDR1)...................................................................... 508
15.2.5 Serial Mode Register (SCSMR1)......................................................................... 509
15.2.6 Serial Control Register (SCSCR1)....................................................................... 511
15.2.7 Serial Status Register (SCSSR1).......................................................................... 515
15.2.8 Serial Port Register (SCSPTR1) .......................................................................... 519
15.2.9 Bit Rate Register (SCBRR1)................................................................................ 523
15.3 Operation .......................................................................................................................... 531
15.3.1 Overview.............................................................................................................. 531
15.3.2 Operation in Asynchronous Mode ....................................................................... 533
Rev. 4.0, 04/00, page xvi of 20
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