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Table 23.12 Clock and Control Signal Timing (HD6417750F167, HD6417750F167I,
HD6417750SF167)
(HD6417750F167: V
HD6417750F167I: V
Item
EXTAL
PLL2
clock input
operating
frequency
PLL2 not
operating
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width t
EXTAL clock output rise time
EXTAL clock input fall time
CKIO clock
PLL2 operating
output
PLL2 not operating
CKIO clock output cycle time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
CKIO clock output rise time
CKIO clock output fall time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
Power-on oscillation settling time
Power-on oscillation settling time/mode
settling
SCK2 reset setup time
SCK2 reset hold time
MD reset setup time
MD reset hold time
5(6(7 assert time
= 3.0 to 3.6 V, V
DDQ
= 3.0 to 3.6 V, V
DDQ
1/2 divider
operating
1/2 divider not
operating
1/2 divider
operating
1/2 divider not
operating
= 1.8 V, T
= –20 to +75°C, C
DD
a
= 1.8 V, T
= –40 to +85°C, C
DD
a
Symbol
Min
f
16
EX
f
8
EX
f
2
EX
f
1
EX
t
18
EXcyc
t
3.5
EXL
3.5
EXH
t
—
EXr
t
—
EXf
f
25
OP
f
1
OP
t
12
cyc
t
1
CKOL1
t
1
CKOH1
t
—
CKOr
t
—
CKOf
t
3
CKOL2
t
3
CKOH2
t
10
OSC1
t
10
OSCMD
t
20
SCK2RS
t
20
SCK2RH
t
3
MDRS
t
20
MDRH
t
20
RESW
= 30 pF
L
= 30 pF)
L
Max
Unit
Figure
55.6
MHz
27.8
55.6
27.8
1000
ns
23.1
—
ns
23.1
—
ns
23.1
4
ns
23.1
4
ns
23.1
83.3
MHz
83.3
MHz
1000
ns
23.2(1)
—
ns
23.2(1)
—
ns
23.2(1)
4
ns
23.2(1)
4
ns
23.2(1)
—
ns
23.2(2)
—
ns
23.2(2)
—
ms
23.3, 23.5
—
ms
23.3, 23.5
—
ns
23.11
—
ns
23.3, 23.5, 23.11
—
t
23.12
cyc
—
ns
23.3, 23.5, 23.12
—
t
23.3, 23.4, 23.5,
cyc
23.6, 23.11
Rev. 4.0, 04/00, page 743 of 850
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