Cpg Register Description; Frequency Control Register (Frqcr) - Hitachi SH7750 series Hardware Manual

Table 10.4 FRQCR Settings and Internal Clock Frequencies
Frequency Division Ratio
FRQCR
(Lower CPU Bus
9 Bits) Clock Clock
H'008 1 1/2
H'00A
H'00C
H'011 1/3
H'013
H'01A 1/4
H'01C
H'023 1/6
H'02C 1/8
H'05A 1/2 1/4
H'05C
H'063 1/6
H'06C 1/8
H'0A3 1/3 1/6
H'0EC 1/4 1/8
Note: * Taking input clock value as 1.
Do not set values other than those shown in the table.
10.4

CPG Register Description

10.4.1

Frequency Control Register (FRQCR)

The frequency control register (FRQCR) is a 16-bit readable/writable register that specifies
use/non-use of clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU
clock, bus clock, and peripheral module clock frequency division ratios. Only word access can be
used on FRQCR.
FRQCR is initialized only by a power-on reset via the 5(6(7 pin. The initial value of each bit is
determined by the clock operating mode.
Peripheral 1/2 Frequency
Module Divider Off
Clock PLL1 Off
1/2 1:1/2:1/2
1/4 1:1/2:1/4
1/8 1:1/2:1/8
1/3 1:1/3:1/3
1/6 1:1/3:1/6
1/4 1:1/4:1/4
1/8 1:1/4:1/8
1/6 1:1/6:1/6
1/8 1:1/8:1/8
1/4 1/2:1/4:1/4
1/8 1/2:1/4:1/8
1/6 1/2:1/6:1/6
1/8 1/2:1/8:1/8
1/6 1/3:1/6:1/6
1/8 1/4:1/8:1/8
Clock Ratio (I:B:P)*
1/2 Frequency 1/2 Frequency
Divider Off Divider On
PLL1 On PLL1 Off
6:3:3 1/2:1/4:1/4
6:3:3/2 1/2:1/4:1/8
6:3:3/4 1/2:1/4:1/16
6:2:2 1/2:1/6:1/6
6:2:1 1/2:1/6:1/12
6:3/2:3/2 1/2:1/8:1/8
6:3/2:3/4 1/2:1/8:1/16
6:1:1 1/2:1/12:1/12
6:3/4:3/4 1/2:1/16:1/16
3:3/2:3/2 1/4:1/8:1/8
3:3/2:3/4 1/4:1/8:1/16
3:1:1 1/4:1/12:1/12
3:3/4:3/4 1/4:1/16:1/16
2:1:1 1/6:1/12:1/12
3/2:3/4:3/4 1/8:1/16:1/16
Rev. 4.0, 04/00, page 203 of 850
1/2 Frequency
Divider On
PLL1 On
3:3/2:3/2
3:3/2:3/4
3:3/2:3/8
3:1:1
3:1:1/2
3:3/4:3/4
3:3/4:3/8
3:1/2:1/2
3:3/8:3/8
3/2:3/4:3/4
3/2:3/4:3/8
3/2:1/2:1/2
3/2:3/8:3/8
1:1/2:1/2
3/4:3/8:3/8