Hitachi SH7750 series Hardware Manual page 583

Superh risc engine
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Bit 6—Character Length (CHR): Selects 7 or 8 bits as the asynchronous mode data length.
Bit 6: CHR
0
1
Note: * When 7-bit data is selected, the MSB (bit 7) of SCFTDR2 is not transmitted.
Bit 5—Parity Enable (PE): Selects whether or not parity bit addition is performed in
transmission, and parity bit checking in reception.
Bit 5: PE
0
1
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/( bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity (even
or odd) specified by the O/( bit.
Bit 4—Parity Mode (O/( ( ( ( ): Selects either even or odd parity for use in parity addition and
checking. The O/( bit setting is only valid when the PE bit is set to 1, enabling parity bit addition
and checking. The O/( bit setting is invalid when parity addition and checking is disabled.
Bit 4: O/( ( ( (
0
1
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
number of 1-bits in the transmit character plus the parity bit is even. In reception, a
check is performed to see if the total number of 1-bits in the receive character plus the
parity bit is even.
2. When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check
is performed to see if the total number of 1-bits in the receive character plus the parity
bit is odd.
Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length.
Bit 3: STOP
0
1
Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character
before it is sent.
2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character
before it is sent.
Rev. 4.0, 04/00, page 572 of 850
Description
8-bit data
7-bit data*
Description
Parity bit addition and checking disabled
Parity bit addition and checking enabled*
Description
1
Even parity*
2
Odd parity*
Description
1
1 stop bit*
2
2 stop bits*
(Initial value)
(Initial value)
(Initial value)
(Initial value)

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