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CKIO
Bank
Precharge-sel
Address
RD/
DQMn
D63–D0
(read)
CKE
Figure 13.36 Burst Read Cycle for Different Bank and Row Address Following Preceding
Refreshing: The bus state controller is provided with a function for controlling synchronous
DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting
the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh
mode, in which the power consumption for data retention is low, can be activated by setting both
the RMODE bit and the RFSH bit to 1.
• Auto-Refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS2–
CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2–CKS0 in RTCOR
should be set so as to satisfy the refresh interval specification for the synchronous DRAM
used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR,
then make the CKS2–CKS0 setting last of all. When the clock is selected by CKS2–CKS0,
RTCNT starts counting up from the value at that time. The RTCNT value is constantly
compared with the RTCOR value, and if the two values are the same, a refresh request is
generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero and
the count-up is restarted. Figure 13.38 shows the auto-refresh cycle timing.
Tc1_A
H/L
c_A
Burst Read Cycle
Tc1_B
H/L
c_B
a1
a2
a3
Rev. 4.0, 04/00, page 367 of 850
a4
b1
b2
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