Hitachi SH7750 series Hardware Manual page 588

Superh risc engine
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Bit 7—Receive Error (ER): Indicates that a framing error or parity error occurred during
reception.
*1
Bit 7: ER
0
1
Notes: 1. The ER flag is not affected and retains its previous state when the RE bit in SCSCR2 is
cleared to 0. When a receive error occurs, the receive data is still transferred to
SCFRDR2, and reception continues.
The FER and PER bits in SCFSR2 can be used to determine whether there is a receive
error in the data read from SCFRDR2.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit
is not checked.
Description
No framing error or parity error occurred during reception
[Clearing conditions]
Power-on reset or manual reset
When 0 is written to ER after reading ER = 1
A framing error or parity error occurred during reception
[Setting conditions]
When the SCIF checks whether the stop bit at the end of the receive
data is 1 when reception ends, and the stop bit is 0*
When, in reception, the number of 1-bits in the receive data plus the
parity bit does not match the parity setting (even or odd) specified by the
O/( bit in SCSMR2
(Initial value)
2
Rev. 4.0, 04/00, page 577 of 850

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