Hitachi SH7750 series Hardware Manual page 726

Table 22.1 Pin Functions (cont)
Pin
No. No. Pin Name
87 V9 VDDQ
88 U9 VSSQ
89 Y9 A9
90 W10 A8
91 Y10 A7
92 Y11 CKIO
93 V10 VDDQ
94 U10 VSSQ
95 W11 CKIO2
96 Y12 A6
97 W12 A5
98 Y13 A4
99 V11 VDDQ
100 U11 VSSQ
101 W13 A3
102 Y14 A2
103 V12 DRAK1
104 U13 DRAK0
105 V13 VDDQ
106 U12 VSSQ
&66
107 W14
&65
108 Y15
109 V14 VDD
110 U14 VSS
5$6
111 W15
5'/&$66/
112 Y16
)5$0(
113 V15 VDDQ
114 U15 VSSQ
Note: * CKIO2 is not connected to PLL2.
Rev. 4.0, 04/00, page 718 of 850
I/O Function
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
O Address
O Clock output
Power IO VDD (3.3 V)
Power IO GND (0 V)
O = CKIO*
O Address
O Address
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
O DMAC1
request
acknowledge
O DMAC0
request
acknowledge
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Chip select 3
O Chip select 2
Power Internal VDD
(1.8 V)
Power Internal GND
(0 V)
5$6
O
O Read/&$6/
)5$0(
Power IO VDD (3.3 V)
Power IO GND (0 V)
SRAM DRAM
Reset
&66
(&66)
&65
(&65)
5$6
2(
Memory Interface
SDRAM PCMCIA MPX
CKIO
CKIO
&66
&65
5$6
&$6 2(
&66
&65
)5$0(