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(1) Cache Control Register (CCR): CCR contains the following bits:
IIX:
IC index enable
ICI:
IC invalidation
ICE:
IC enable
OIX: OC index enable
ORA: OC RAM enable
OCI: OC invalidation
CB:
Copy-back enable
WT:
Write-through enable
OCE: OC enable
Longword access to CCR can be performed from H'FF00 001C in the P4 area and H'1F00 001C in
area 7. The CCR bits are used for the cache settings described below. Consequently, CCR
modifications must only be made by a program in the non-cached P2 area. After CCR is updated,
an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least
four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or
U0 area should be located at least eight instructions after the CCR update instruction.
• IIX: IC index enable bit
0: Address bits [12:5] used for IC entry selection
1: Address bits [25] and [11:5] used for IC entry selection
• ICI: IC invalidation bit
When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit always returns
0 when read.
• ICE: IC enable bit
Indicates whether or not the IC is to be used. When address translation is performed, the IC
cannot be used unless the C bit in the page management information is also 1.
0: IC not used
1: IC used
• OIX: OC index enable bit
0: Address bits [13:5] used for OC entry selection
1: Address bits [25] and [12:5] used for OC entry selection
• ORA: OC RAM enable bit
When the OC is enabled (OCE = 1), the ORA bit specifies whether the 8 kbytes from entry
128 to entry 255 and from entry 384 to entry 511 of the OC are to be used as RAM. When the
OC is not enabled (OCE = 0), the ORA bit should be cleared to 0.
0: 16 kbytes used as cache
1: 8 kbytes used as cache, and 8 kbytes as RAM
Rev. 4.0, 04/00, page 63 of 850
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