Hitachi SH7750 series Hardware Manual page 506

CLK
DBREQ
BAVL
TR
A25–A0
RA CA
D63–D0
D0 D1 D2 D3
RAS,
BA RD
CAS, WE
TDACK
ID1, ID0
10
No DTR cycle, so requests can be made at any time
Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/
External Bus → → → → External Device Data Transfer/
Direct Data Transfer Request to Channel 2 without Using Data Bus
Rev. 4.0, 04/00, page 495 of 850