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Valid only for SRAM interface and burst ROM interface:
Bit 4n + 2—Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles
inserted in the setup time from the address until assertion of the read/write strobe.
Bit 4n + 2: AnS0
0
1
Valid only for SRAM interface and burst ROM interface:
Bits 4n + 1 and 4n—Area n (6 to 0) Data Hold Time (AnH1, AnH0): When writing, these bits
specify the number of cycles to be inserted in the hold time from negation of the write strobe.
When reading, they specify the number of cycles to be inserted in the hold time from the data
sampling timing.
Bit 4n + 1: AnH1
0
1
13.2.6
Memory Control Register (MCR)
The memory control register (MCR) is a 32-bit readable/writable register that specifies 5$6 and
&$6 timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address
multiplexing, and refresh control. This enables DRAM and synchronous DRAM to be connected
without using external circuitry.
MCR is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. Bits RASD, MRSET, TRC2–0, TPC2–0, RCD1–0, TRWL2–0, TRAS2–0, BE,
SZ1–0, AMXEXT, AMX2–0, and EDOMODE are written in the initialization following a power-
on reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the
same values should be written to the other bits so that they remain unchanged. When using DRAM
or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is
completed.
Rev. 4.0, 04/00, page 292 of 850
Waits Inserted in Setup
0
1
Bit 4n: AnH0
0
1
0
1
Waits Inserted in Hold
0
1
2
3
(Initial value)
(n = 6 to 0)
(Initial value)
(n = 6 to 0)
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