Table of Contents
Advertisement
Table E.1
Pin States in Reset, Power-Down State, and Bus-Released State (cont)
Signal Name
TDO
TMS
TCK
TDI
7567
10
CKIO2*
5'5*
10
10
RD/:55*
&.,25(1%
Notes: I: Input
O: Output
H: High-level output
L: Low-level output
Z: High-impedance
K: Output state held
1. Output when area 2 DRAM is used.
2. Output when area 5 PCMCIA is used.
3. Output when area 6 PCMCIA is used.
4. Depends on refresh and DMAC operations.
5. Z (I) or O (refresh), depending on register setting (BCR1.HIZCNT).
6. Depends on refresh operation.
7. Z (I) or H (state held), depending on register setting (BCR1.HIZMEM).
8. Z or O, depending on register setting (STBCR.PHZ).
9. Output when refreshing is set.
10. Operation in respective state when &.,25(1% = 0; Z when &.,25(1% = 1.
11. Z or O, depending on register setting (FRQCR.CKOEN).
12. Pulled up or not pulled up, depending on register setting (STBCR.PPU).
13. Pulled up or not pulled up, depending on register setting (BCR1.IPUP).
14. Pulled up or not pulled up, depending on register setting (BCR1.OPUP).
15. Not pulled up.
16. Pulled up. However, cannot be used for mode pin pull-up in a power-on reset. Pull up
or down outside the SH-4.
Rev. 4.0, 04/00, page 828 of 850
Reset
(Power-On)
I/O
Master Slave
O
O
O
16
16
16
I*
I*
I*
16
16
16
I*
I*
I*
16
16
16
I*
I*
I*
16
16
16
I*
*
I
I*
O
O
O
16
O
H
Z*
16
O
H
Z*
I
I
I
Reset
(Manual)
Master Slave Sleep Standby
O
O
O
16
16
16
I*
I*
I*
16
16
16
I*
I*
I*
16
16
16
I*
I*
I*
16
16
16
I*
I*
I*
11
11
ZO*
ZO*
ZO*
6
14
4
O*
Z*
O*
14
4
H
Z*
O*
I
I
I
Bus
Released Notes
O
O
16
16
I*
I*
16
16
I*
I*
16
16
I*
I*
16
16
I*
I*
11
11
11
ZO*
ZO*
14
5
14
5
Z*
O*
Z*
O*
14
7
14
Z*
H*
Z*
I
I
H-UDI
H-UDI
H-UDI
H-UDI
H-UDI
Advertisement
Table of Contents
