On-Chip Peripheral Module Interrupts - Hitachi SH7750 series Hardware Manual

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Table 19.4 SH7750 ,5/6

On-Chip Peripheral Module Interrupts

On-chip peripheral module interrupts are generated by the following nine modules:

• Hitachi user debug interface (H-UDI)

• Direct memory access controller (DMAC)

• Timer unit (TMU)

• Realtime clock (RTC)

• Serial communication interface (SCI)

• Serial communication interface with FIFO (SCIF)

• Bus state controller (BSC)

• Watchdog timer (WDT)

• I/O port (GPIO)

Not every interrupt source is assigned a different interrupt vector, bus sources are reflected in the

interrupt event register (INTEVT), so it is easy to identify sources by using the INTEVT register

value as a branch offset in the exception handling routine.

A priority level from 15 to 0 can be set for each module by means of interrupt priority registers A

to C (IPRA–IPRC).

The interrupt mask bits (I3–I0) in the status register (SR) are not affected by on-chip peripheral

module interrupt handling.

On-chip peripheral module interrupt source flag and interrupt enable flag updating should only be

carried out when the BL bit in the status register (SR) is set to 1. To prevent acceptance of an

erroneous interrupt from an interrupt source that should have been updated, first read the on-chip

peripheral register containing the relevant flag, then clear the BL bit to 0. This will secure the

necessary timing internally. When updating a number of flags, there is no problem if only the

,5/3 Pins and Interrupt Levels (When IRLM = 1)

Interrupt Priority Level

Interrupt Request

Rev. 4.0, 04/00, page 665 of 850

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