Hitachi SH7750 series Hardware Manual page 782

CKIO
BANK
Precharge-sel
Addr
CSn
RD/WR
RAS
CASS
DQMn
D63–D0
(write)
BS
CKE
DACKn
(SA: IO → memory)
Figure 23.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands,
Rev. 4.0, 04/00, page 774 of 850
Tr Trw Tc1
t
AD
Row
t
AD
Row
H/L
Row c0
t
CSD
t
RWD
t
t
RASD
RASD
t
CASD2
t
CASD2
t
DQMD
t
WDD
t
WDD
t
BSD
t
DACD
Burst (RCD = 1, TRWL = 2)
Tc2 Tc3 Tc4
t
RWD
t
CASD2
t
WDD
d0 d1 d2
t
BSD
t
DACD
Trwl Trwl
t
AD
t
CSD
t
DQMD
d3