Hitachi SH7750 series Hardware Manual page 739

Table 22.2 Pin Functions (cont)
Pin
No. Pin Name
169 VDD
170 VSS
171 A18
172 A19
173 A20
174 A21
175 A22
176 A23
177 VDDQ
178 VSSQ
179 A24
180 A25
181 MD3/&(5$
182 MD4/&(5%
183 MD5/5$65
184 DACK0
185 DACK1
186 A0
187 VDDQ
188 VSSQ
189 A1
190 STATUS0
191 STATUS1
192 MD6/
,2,649
$6(%5./
193
BRKACK
194 TDO
I/O Function
Power Internal VDD
(1.8 V)
Power Internal GND
(0 V)
O Address
O Address
O Address
O Address
O Address
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
I/O Mode/
PCMCIA-CE
I/O Mode/
PCMCIA-CE
I/O Mode/5$6
(DRAM)
O DMAC0 bus
acknowledge
O DMAC1 bus
acknowledge
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Status
O Status
I Mode/,2,649
(PCMCIA)
I/O Pin break/
acknowledge
)
(H-UDI
O Data out
(H-UDI)
SRAM DRAM
Reset
MD3
MD4
5$65
MD5
MD6
Memory Interface
SDRAM PCMCIA MPX
&(5$
&(5%
,2,649
Rev. 4.0, 04/00, page 731 of 850