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Bit 15: TRWL2
0
1
Note: * Inhibited in RAS down mode.
Bits 12 to 10—CAS-Before-RAS Refresh 5$6
DRAM interface is set, these bits set the 5$6 assertion period in CAS-before-RAS refreshing.
When the synchronous DRAM interface is set, the bank active command is not issued for a period
of TRC* + TRAS after an auto-refresh command is issued.
Bit 12: TRAS2
Bit 11: TRAS1
0
0
1
1
0
1
Note: * Bits 29 to 27: RAS precharge interval at end of refresh.
Bit 9—Burst Enable (BE): Specifies whether burst access is performed on DRAM interface. In
synchronous DRAM access, burst access is always performed regardless of the specification of
this bit. The DRAM transfer mode depends on EDOMODE.
Rev. 4.0, 04/00, page 296 of 850
Bit 14: TRWL1
0
1
0
1
Bit 10: TRAS0
0
1
0
1
0
1
0
1
Bit 13: TRWL0
0
1
0
1
0
1
0
1
5$6 Assertion Period (TRAS2–TRAS0): When the
5$6
5$6
5$6
5$6
5$6/DRAM
5$6
Assertion Period
2
3
4
5
6
7
8
9
Write Precharge ACT Delay Time
1 (Initial value)
2
3*
4*
5*
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Command
Interval after
Synchronous
DRAM Refresh
4 + TRC*
5 + TRC
6 + TRC
7 + TRC
8 + TRC
9 + TRC
10 + TRC
11 + TRC
(Initial value)
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