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Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name: TRWL2 TRWL1 TRWL0
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Bit 31—RAS Down (RASD): Sets RAS down mode. When RAS down mode is used, set BE to 1.
Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3 are both
designated as synchronous DRAM interface.
Bit 31: RASD
0
1
Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2–DMAIW0 to 000
and bits A3IW2–A3IW0 to 000.
Bit 30—Mode Register Set (MRSET): Set when a synchronous DRAM mode register setting is
used. See Power-On Sequence in section 13.3.5, Synchronous DRAM Interface.
Bit 30: MRSET
0
1
31
30
RASD
MRSET
0
0
R/W
R/W
23
22
TCAS
—
0
0
R/W
R
15
14
0
0
R/W
R/W
7
6
SZ0
AMXEXT AMX2
0
0
R/W
R/W
Description
Normal mode
RAS down mode
Description
All-bank precharge
Mode register setting
29
28
TRC2
TRC1
0
0
R/W
R/W
21
20
TPC2
TPC1
0
0
R/W
R/W
13
12
TRAS2
TRAS1
0
0
R/W
R/W
5
4
AMX1
AMX0
0
0
R/W
R/W
27
26
TRC0
—
0
0
R/W
R
19
18
TPC0
—
0
0
R/W
R
11
10
TRAS0
0
0
R/W
R/W
3
2
RFSH
RMODE
0
0
R/W
R/W
Rev. 4.0, 04/00, page 293 of 850
25
24
—
—
0
0
R
R
17
16
RCD1
RCD0
0
0
R/W
R/W
9
8
BE
SZ1
0
0
R/W
R/W
1
0
EDO
MODE
0
0
R/W
R/W
(Initial value)
(Initial value)
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