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14.2.3
DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 32-bit readable/writable registers
that specify the transfer count for the corresponding channel (byte count, word count, longword
count, quadword count, or 32-byte count). Specifying H'000001 gives a transfer count of 1, while
H'000000 gives the maximum setting, 16,777,216 (16M) transfers. During DMAC operation, the
remaining number of transfers is shown.
Bits 31–24 of these registers are reserved; they are always read as 0, and should only be written
with 0.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode and deep sleep mode.
In DDT mode, DTR format [55:48] is set in DMATCR0 [7:0]
31
30
0
0
R
R
23
22
—
—
R/W
R/W
15
14
—
—
R/W
R/W
7
6
—
—
R/W
R/W
29
28
0
0
R
R
21
20
—
—
R/W
R/W
13
12
—
—
R/W
R/W
5
4
—
—
R/W
R/W
27
26
0
0
R
R
19
18
—
—
R/W
R/W
11
10
—
—
R/W
R/W
3
2
—
—
R/W
R/W
Rev. 4.0, 04/00, page 427 of 850
25
24
0
0
R
R
17
16
—
—
R/W
R/W
9
8
—
—
R/W
R/W
1
0
—
—
R/W
R/W
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